The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2023

Filed:

Jun. 09, 2020
Applicant:

Shenzhen Goodix Technology Co., Ltd., Shenzhen, CN;

Inventors:

Guofeng Yao, Shenzhen, CN;

Jian Shen, Shenzhen, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H10B 63/00 (2023.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 23/528 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H10B 63/30 (2023.02); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/26513 (2013.01); H01L 21/28035 (2013.01); H01L 23/528 (2013.01); H01L 29/0847 (2013.01); H01L 29/42376 (2013.01); H01L 29/66568 (2013.01); H10B 63/80 (2023.02); H10N 70/021 (2023.02); H10N 70/826 (2023.02); H01L 21/02255 (2013.01);
Abstract

The present disclosure provides a 1T1R resistive random access memory and a manufacturing method thereof, and a device. The 1T1R resistive random access memory includes: a memory cell array composed of multiple 1T1R resistive random access memory cells, each 1T1R resistive random access memory cell including a transistor and a resistance switching device (). The transistor includes a channel layer (), a gate layer () insulated from the channel layer (), and a drain layer () and a source layer () disposed on the channel layer (), and the drain layer () and the source layer () are vertically distributed on the channel layer (). The resistance change device () is disposed near the drain layer (). The disclosure reduces the area of a transistor, thereby significantly improving the memory density of the resistive random access memory.


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