The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2023

Filed:

Jun. 07, 2022
Applicant:

Ambarella International Lp, Santa Clara, CA (US);

Inventor:

Yueh Chun Cheng, Cupertino, CA (US);

Assignee:

Ambarella International LP, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/1252 (2006.01); G05F 1/56 (2006.01); H03K 3/03 (2006.01); H03K 3/011 (2006.01); H03L 1/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1252 (2013.01); G05F 1/56 (2013.01); H03K 3/011 (2013.01); H03K 3/0315 (2013.01); H03K 3/0322 (2013.01); H03L 1/00 (2013.01);
Abstract

An apparatus comprises a first circuit, a second circuit, a first transistor, a second transistor, a third transistor, a first programmable resistance, and a second programmable resistance. The first circuit may be configured to generate a reference signal and a bias signal in response to a supply voltage and a first input signal. The first circuit generally provides supply noise rejection to variations in the supply voltage. The second circuit may be connected to the first circuit and a ring oscillator. The first transistor may be connected to the first circuit and configured to set a first reference current of the first circuit based on the first input signal and the first programmable resistance. The second transistor may be connected in parallel with the first transistor. The second transistor is generally diode-connected. The third transistor may be connected to the first circuit and configured to set a second reference current of the first circuit based on the first input signal and the second programmable resistance. The first circuit generally forms a current mirror with the second circuit. The second circuit may be configured to provide a programmable current ratio for the current mirror based on a value of a second input signal.


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