The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2023

Filed:

Jul. 13, 2021
Applicant:

Macom Technology Solutions Holdings, Inc., Lowell, MA (US);

Inventors:

James Joseph Brogle, Merrimac, MA (US);

Joseph Gerard Bukowski, Derry, NH (US);

Margaret Mary Barter, Lowell, MA (US);

Timothy Edward Boles, Tyngsboro, MA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H01L 23/66 (2006.01); H01L 29/868 (2006.01); H01L 27/08 (2006.01); H01L 21/822 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0676 (2013.01); H01L 21/2253 (2013.01); H01L 21/2254 (2013.01); H01L 21/26513 (2013.01); H01L 23/66 (2013.01); H01L 27/0814 (2013.01); H01L 29/868 (2013.01); H01L 21/822 (2013.01); H01L 29/6609 (2013.01); H01L 2223/6627 (2013.01); H01L 2223/6666 (2013.01); H01L 2223/6683 (2013.01);
Abstract

A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a method of manufacture of a monolithic diode limiter includes providing an N-type semiconductor substrate, providing an intrinsic layer on the N-type semiconductor substrate, implanting a first P-type region to a first depth into the intrinsic layer, implanting a second P-type region to a second depth into the intrinsic layer, and forming at least one passive circuit element over the intrinsic layer. The method can also include forming an insulating layer on the intrinsic layer, forming a first opening in the insulating layer, and forming a second opening in the insulating layer. The method can also include implanting the first P-type region through the first opening and implanting the second P-type region through the second opening.


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