The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2023

Filed:

Dec. 12, 2018
Applicant:

Siemens Aktiengesellschaft, Munich, DE;

Inventors:

Thomas Hinterstoisser, Bisamberg, AT;

Martin Matschnig, Tulin, AT;

Herbert Taucher, Vienna, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/323 (2020.01); G06F 30/327 (2020.01); G06N 3/08 (2023.01); G06N 3/063 (2023.01);
U.S. Cl.
CPC ...
G06N 3/08 (2013.01); G06F 30/323 (2020.01); G06F 30/327 (2020.01); G06N 3/063 (2013.01);
Abstract

A method for realizing an artificial neural network via an electronic integrated circuit (FPGA), wherein artificial neurons grouped into different interlinked layers for the artificial neural network, where a functional description is created for each neuron of the artificial neural network, taking into account a specifiable starting weighting, a synthesis is performed for each neuron based on the associated functional description with the associated specified starting weighting, a network list is determined as the synthesis result, in which at least a base element and a starting configuration belonging to the base element are stored for each neuron, a base element is formed as a lookup table (LUT) unit and an associated dynamic configuration cell, in which a current configuration for the LUT unit or the base element is stored, and where the network list is implemented as a starting configuration of the artificial neural network in the electronic integrated circuit.


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