The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2023

Filed:

Jul. 01, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Augusto Vega, Mount Vernon, NY (US);

Alper Buyuktosunoglu, White Plains, NY (US);

Hubertus Franke, Cortlandt Manor, NY (US);

John-David Wellman, Hopewell Junction, NY (US);

Pradip Bose, Yorktown Heights, NY (US);

Robert Matthew Senger, Tarrytown, NY (US);

Aporva Amarnath, Ann Arbor, MI (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/48 (2006.01); G06Q 20/14 (2012.01); G06F 16/901 (2019.01);
U.S. Cl.
CPC ...
G06F 9/4893 (2013.01); G06F 16/9024 (2019.01); G06Q 20/145 (2013.01); G06F 2209/486 (2013.01);
Abstract

Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.


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