The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Jun. 23, 2020
Applicant:

Murata Manufacturing Co., Ltd., Kyoto, JP;

Inventors:

Saneaki Ariumi, Kyoto, JP;

Tomoshige Furuhi, Kyoto, JP;

Sho Suzuki, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01Q 1/38 (2006.01); H05K 3/46 (2006.01); H01P 3/08 (2006.01); H01Q 13/08 (2006.01); H05K 1/09 (2006.01); H05K 3/38 (2006.01);
U.S. Cl.
CPC ...
H05K 3/46 (2013.01); H01P 3/08 (2013.01); H01Q 1/38 (2013.01); H01Q 13/08 (2013.01); H05K 1/09 (2013.01); H05K 3/38 (2013.01);
Abstract

The insertion loss of a multilayer substrate and an antenna element is reduced. A multilayer substrate according to an embodiment of the present disclosure includes a multilayer body, a wire conductor, and a first ground electrode. The multilayer body is formed by dielectric layers being layered. The wire conductor is formed in the multilayer body, and a radio frequency signal passes through the wire conductor. The first ground electrode is formed in or on the multilayer body and includes a first surface that faces the wire conductor. The first surface includes a first region and a second region. The surface roughness of the first region is lower than the surface roughness of the second region. The first region overlaps at least part of the wire conductor in plan view in a direction normal to the first ground electrode.


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