The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Jan. 10, 2022
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventors:

Yi-Ting Liu, Hsinchu, TW;

Jian Liu, Suzhou, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/03 (2006.01); H04B 1/16 (2006.01); H04L 25/02 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03878 (2013.01); H04B 1/16 (2013.01); H04L 25/0292 (2013.01);
Abstract

A receiving circuit of a deserializer is provided. The receiving circuit of the deserializer receives an input signal and includes: a signal receiving terminal for receiving the input signal; a link equalizer circuit (LEQ) having a first input terminal coupled to the signal receiving terminal; and an out-of-band signaling (OOBS) circuit having a second input terminal coupled to the signal receiving terminal; a first resistor coupled between the signal receiving terminal and a first reference voltage; and a second resistor coupled between the signal receiving terminal and a second reference voltage; and a buffer circuit having a third input terminal and an output terminal, wherein the third input terminal receives a voltage, and the output terminal is coupled to the LEQ or the OOBS circuit. The first input terminal of the LEQ and the second input terminal of the OOBS circuit are not electrically coupled, and the voltage is adjustable.


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