The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Dec. 24, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jintae Kim, Daejeon, KR;

Byounggon Kang, Seoul, KR;

Changbeom Kim, Tongyeong-si, KR;

Ha-Young Kim, Seoul, KR;

Yongeun Cho, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01); H01L 27/02 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 27/092 (2006.01); H01L 23/522 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0372 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01);
Abstract

A semiconductor device includes a flip flop cell. The flip flop cell is formed on a semiconductor substrate, includes a flip flop circuit, and comprises a scan mux circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan mux circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices which together output a resulting signal for that circuit based on inputs, is a sub-circuit of the flip flop circuit, and occupies a continuously-bounded area of the flip flop circuit from a plan view. At least a first sub-circuit and a second sub-circuit of the sub-circuits overlap from the plan view in a first overlap region, the first overlap region including part of a first continuously-bounded area for the first sub-circuit and part of a second continuously-bounded area for the second sub-circuit.


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