The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Jan. 31, 2022
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventors:

Kazumi Takagiwa, Matsumoto, JP;

Hitoshi Sumida, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/808 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/808 (2013.01); H01L 29/4175 (2013.01); H01L 29/42312 (2013.01); H01L 29/66681 (2013.01);
Abstract

A semiconductor device includes: a semiconductor layer of a first conductivity-type; a well region of a second conductivity-type provided at an upper part of the semiconductor layer; a base region of the second conductivity-type provided at an upper part of the well region; a carrier supply region of the first conductivity-type provided at an upper part of the base region; a drift region of the first conductivity-type provided separately from the base region; a carrier reception region of the first conductivity-type provided at an upper part of the drift region; a gate electrode provided on a top surface of the well region interposed between the base region and the drift region via a gate insulating film; and a punch-through prevention region of the second conductivity-type provided at the upper part of the well region and having an impurity concentration different from the impurity concentration of the base region.


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