The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Nov. 06, 2020
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Hidekazu Umeda, Osaka, JP;

Kazuhiro Kaibara, Osaka, JP;

Satoshi Tamura, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/80 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78 (2013.01); H01L 29/0661 (2013.01); H01L 29/2003 (2013.01); H01L 29/4238 (2013.01); H01L 29/42316 (2013.01); H01L 29/7786 (2013.01); H01L 29/06 (2013.01); H01L 29/10 (2013.01); H01L 29/1066 (2013.01); H01L 29/1083 (2013.01); H01L 29/20 (2013.01); H01L 29/41758 (2013.01); H01L 29/4236 (2013.01);
Abstract

A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 μm-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.


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