The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Dec. 30, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sunguk Jang, Hwaseong-si, KR;

Seokhoon Kim, Suwon-si, KR;

Seung Hun Lee, Hwaseong-si, KR;

Yang Xu, Suwon-si, KR;

Jeongho Yoo, Jeongnam-si, KR;

Jongryeol Yoo, Osan-si, KR;

Youngdae Cho, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/762 (2006.01); H01L 21/225 (2006.01); H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/762 (2013.01); H01L 21/02164 (2013.01); H01L 21/02181 (2013.01); H01L 21/02225 (2013.01); H01L 21/2253 (2013.01); H01L 21/76229 (2013.01); H01L 21/76232 (2013.01); H01L 29/165 (2013.01); H01L 29/42316 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01);
Abstract

Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.


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