The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2023
Filed:
Jul. 26, 2021
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventor:
Ji Eun Kim, Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 11/4094 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 8/12 (2006.01); G11C 8/18 (2006.01); H01L 25/065 (2023.01); G11C 7/12 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4094 (2013.01); G11C 8/12 (2013.01); G11C 8/18 (2013.01); G11C 11/408 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 7/06 (2013.01); G11C 7/12 (2013.01); H01L 25/0657 (2013.01);
Abstract
A semiconductor memory device may include a core circuit including a plurality of memory cell arrays electrically connected between a plurality of row lines and a plurality of column lines, and a column path control circuit configured to generate a preliminary column pulse from a command signal irrelevant to a column address signal, to generate a main column pulse in response to an enable time point of the column address signal and an enable time point of the preliminary column pulse, and to enable an access target column line among the plurality of column lines.