The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Nov. 27, 2018
Applicant:

Minima Processor Oy, Oulu, FI;

Inventor:

Navneet Gupta, Oulu, FI;

Assignee:

Minima Processor Oy, Espoo, FI;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/394 (2020.01); H03K 5/13 (2014.01); H03K 5/19 (2006.01); G06F 119/12 (2020.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/394 (2020.01); H03K 5/13 (2013.01); H03K 5/19 (2013.01); G06F 2119/12 (2020.01); H03K 19/20 (2013.01);
Abstract

Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units. At least some of said plurality of processing paths comprise logic units belonging to said third class but have monitoring units associated with them.


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