The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Jun. 26, 2019
Applicant:

Nordic Semiconductor Asa, Trondheim, NO;

Inventors:

Ronan Barzic, Trondheim, NO;

Berend Dekens, Trondheim, NO;

Frank Aune, Trondheim, NO;

Anders Nore, Trondheim, NO;

Assignee:

Nordic Semiconductor ASA, Trondheim, NO;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/85 (2013.01); G06F 21/54 (2013.01); G06F 21/56 (2013.01); G06F 21/60 (2013.01); G06F 21/64 (2013.01);
U.S. Cl.
CPC ...
G06F 21/85 (2013.01); G06F 21/54 (2013.01); G06F 21/567 (2013.01); G06F 21/602 (2013.01); G06F 21/64 (2013.01);
Abstract

An integrated-circuit device comprises a processor, a peripheral component, a bus system, connected to the processor and to the peripheral component, and configured to carry bus transactions; and hardware filter logic. The bus system is configured to carry security-state signals for distinguishing between secure and non-secure bus transactions. The peripheral component comprises a register interface, accessible over the bus system, and comprising a hardware register and a direct-memory-access (DMA) controller for initiating bus transactions on the bus system. The peripheral component supports a secure-in-and-non-secure-out state in which the hardware filter logic is configured to prevent non-secure bus transactions from accessing the hardware register of the peripheral component, but to allow secure bus transactions to access the peripheral component. The peripheral component is configured to allow an incoming secure bus transaction to access the hardware register and to initiate a bus transaction as non-secure.


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