The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Dec. 28, 2020
Applicant:

Ati Technologies Ulc, Markham, CA;

Inventors:

Nippon Raval, Markham, CA;

Philip Ng, Toronto, CA;

Rostislav S. Dobrin, Toronto, CA;

Assignee:

ATI TECHNOLOGIES ULC, Markham, CA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01); G06F 13/28 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 12/063 (2013.01); G06F 13/28 (2013.01); G06F 13/4221 (2013.01); G06F 2212/206 (2013.01);
Abstract

Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One apparatus includes an input/output memory management unit (IOMMU) comprising: a plurality of memory-mapped input/output (MMIO) registers that map memory address spaces belonging to the IOMMU and at least a second IOMMU; and hardware control logic operative to: synchronize the plurality of MMIO registers of the at least the second IOMMU; receive, from a peripheral component endpoint coupled to the IOMMU, a direct memory access (DMA) request, the DMA request to a memory address space belonging to the at least the second IOMMU; access the plurality of MMIO registers of the IOMMU based on context data of the DMA request; and access, from the IOMMU, a function assigned to the memory address space belonging to the at least the second IOMMU based on the accessed plurality of MMIO registers.


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