Memory, memory controlling method and system

Abstract

A memory, a method controlling method and a system are disclosed. The memory includes: an array of memory cells; a power manager; an instruction decoder; a controller; and an I/O interface, including a chip select pin. In the standby state, the instruction decoder and controller are enabled; in the power-down state, the instruction decoder is enabled; and in the deep power-down state, they are all disabled. In response to receiving a chip select signal, the memory enters the power-down state from the deep power-down state. The memory of the present disclosure provides the deep power-down state that disables the decoder, and the memory in the deep power-down state exits directly to the power-down state to achieve some functions without enabling all components, thereby reducing power consumption.