The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Jun. 03, 2019
Applicant:

Robert Bosch Gmbh, Stuttgart, DE;

Inventors:

Juergen Schirmer, Heidelberg, DE;

Andre Guntoro, Weil der Stadt, DE;

Armin Runge, Renningen, DE;

Christoph Schorn, Leonberg, DE;

Jaroslaw Topp, Renningen, DE;

Sebastian Vogel, Schaidt, DE;

Assignee:

ROBERT BOSCH GMBH, Stuttgart, DE;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/3287 (2019.01); G06F 1/3237 (2019.01); G06N 3/04 (2023.01); G06N 3/063 (2023.01); G06V 20/56 (2022.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/3237 (2013.01); G06N 3/04 (2013.01); G06N 3/063 (2013.01); G06V 20/56 (2022.01);
Abstract

A hardware architecture for an artificial neural network ANN. The ANN includes a consecutive series made up of an input layer, multiple processing layers, and an output layer. Each layer maps a set of input variables onto a set of output variables, and output variables of the input layer and of each processing layer are input variables of the particular layer that follows in the series. The hardware architecture includes a plurality of processing units. The implementation of each layer is split among at least two of the processing units, and at least one resettable switch-off device is provided via which at least one processing unit is selectively deactivatable, independently of the input variables supplied to it, in such a way that at least one further processing unit remains activated in all layers whose implementation is contributed to by this processing unit.


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