The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Sep. 10, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Eunhye Oh, Yongin-si, KR;

Hyochul Shin, Seoul, KR;

Jinwoo Park, Hwaseong-si, KR;

Sungno Lee, Hwaseong-si, KR;

Younghyo Park, Hwaseong-si, KR;

Yongki Lee, Suwon-si, KR;

Heejune Lee, Suwon-si, KR;

Youngjae Cho, Hwaseong-si, KR;

Michael Choi, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H03K 5/24 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2884 (2013.01); H03K 5/24 (2013.01); H03M 1/124 (2013.01);
Abstract

A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.


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