The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2023

Filed:

May. 14, 2021
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Paolo Ferrari, Gallarate, IT;

Flavio Francesco Villa, Milan, IT;

Lucia Zullino, Milan, IT;

Andrea Nomellini, Milan, IT;

Luca Seghizzi, Milan, IT;

Luca Zanotti, Agrate Brianza, IT;

Bruno Murari, Monza, IT;

Martina Scolari, Milan, IT;

Assignee:

STMICROELECTRONICS S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 10/855 (2023.01); H10N 10/01 (2023.01); H10N 10/17 (2023.01);
U.S. Cl.
CPC ...
H10N 10/855 (2023.02); H10N 10/01 (2023.02); H10N 10/17 (2023.02);
Abstract

A method of fabricating a thermoelectric converter that includes providing a layer of a Silicon-based material having a first surface and a second surface, opposite to and separated from the first surface by a Silicon-based material layer thickness; forming a plurality of first thermoelectrically active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectrically active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first and second thermoelectrically active elements are formed to extend through the Silicon-based material layer thickness, from the first surface to the second surface; forming electrically conductive interconnections in correspondence of the first surface and of the second surface of the layer of Silicon-based material, for electrically interconnecting the plurality of first thermoelectrically active elements and the plurality of second thermoelectrically active elements, and forming an input electrical terminal and an output electrical terminal electrically connected to the electrically conductive interconnections, wherein the first thermoelectric semiconductor material and the second thermoelectric semiconductor material comprise Silicon-based materials selected among porous Silicon or polycrystalline SiGe or polycrystalline Silicon.


Find Patent Forward Citations

Loading…