The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2023

Filed:

Jan. 28, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Geet Govind Modi, Cupertino, CA (US);

Sumantra Seth, Bangalore, IN;

Vikram Sharma, Bangalore, IN;

Shankar Ramakrishnan, Bangalore, IN;

Raghu Ganesan, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/38 (2015.01); H04L 5/16 (2006.01); H04L 7/033 (2006.01); H04L 7/06 (2006.01); H04L 7/00 (2006.01); H03K 19/173 (2006.01); H04L 7/04 (2006.01); H03K 19/17784 (2020.01);
U.S. Cl.
CPC ...
H04L 7/033 (2013.01); H03K 19/1737 (2013.01); H03K 19/17784 (2013.01); H04L 7/0079 (2013.01); H04L 7/0091 (2013.01); H04L 7/048 (2013.01); H04L 7/065 (2013.01);
Abstract

A physical layer transceiver and a network node including the transceiver. The transceiver includes a media independent interface, a converter circuit block comprising circuitry configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry including power management circuitry and reset circuitry are provided. The transceiver further includes at least one single event effect (SEE) monitor, such as an ambience monitor, a configuration register monitor, a state machine monitor, or a phase locked loop (PLL) lock monitor, configured to detect and respond to an SEE event in the transceiver.


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