The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2023

Filed:

Feb. 15, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Mustapha El Markhi, Richardson, TX (US);

Alejandro Vera, Wylie, TX (US);

Tonmoy Roy, Dallas, TX (US);

Rohit Bhan, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02J 7/00 (2006.01);
U.S. Cl.
CPC ...
H02J 7/0031 (2013.01); H02J 7/00 (2013.01); H02J 7/00302 (2020.01); H02J 7/00304 (2020.01);
Abstract

Aspects of the disclosure provide for a circuit. In at least some examples, the circuit includes a logic circuit, a first comparator, a second comparator, and an AND logic circuit. The logic circuit has an output and the first comparator has a first input coupled to an input voltage (VIN) pin, a second input configured to receive a Vin under voltage lockout (VINUVLO) threshold value, and an output. The second comparator has a first input coupled to a power middle (PMID) pin, a second input coupled to a battery pin, and an output and the AND logic circuit has a first input coupled to the output of the logic circuit, a second input coupled to the output of the first comparator, a third input coupled to the output of the second comparator, and an output coupled to an input of a field-effect transistor (FET) control circuit.


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