The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2023

Filed:

Jan. 28, 2021
Applicant:

Witricity Corporation, Watertown, MA (US);

Inventors:

Conor Rochford, Newton, MA (US);

Milisav Danilovic, Watertown, MA (US);

Assignee:

WiTricity Corporation, Watertown, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 7/20 (2006.01); H02H 1/00 (2006.01); H02M 1/08 (2006.01); H02M 7/06 (2006.01); H02H 7/125 (2006.01); H02J 50/12 (2016.01); H02J 7/02 (2016.01);
U.S. Cl.
CPC ...
H02H 7/20 (2013.01); H02H 1/0007 (2013.01); H02H 7/125 (2013.01); H02M 1/08 (2013.01); H02M 7/06 (2013.01); H02J 7/02 (2013.01); H02J 50/12 (2016.02);
Abstract

The disclosure features circuits and methods for protecting transistors of a wireless power receiver, which can be controlled by gate drivers powered by an auxiliary power source. The circuit can include a comparator configured to generate a signal indicating a comparison of a value of the auxiliary power source to a predetermined threshold, and a fault latch coupled to the comparator. The fault latch can be configured to trigger based on the generated signal and transmit a signal to respective inputs of the gate drivers to cause a latched-on state of respective gates of the transistors. Switches respectively coupled to the gate drivers can be configured to disconnect respective outputs of the gate drivers from the respective transistor gates. Gate hold-up circuits respectively coupled to the respective transistor gates can be configured to maintain the latched-on state of the respective transistor gates for a period of time.


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