The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2023

Filed:

Apr. 30, 2019
Applicant:

Nanyang Technological University, Singapore, SG;

Inventors:

Kwen Siong Chong, Singapore, SG;

Bah Hwee Gwee, Singapore, SG;

Weng Geng Ho, Singapore, SG;

Ne Kyaw Zaw Lwin, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/098 (2006.01); H01L 23/52 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/098 (2013.01); H01L 23/52 (2013.01); H01L 29/0615 (2013.01); H01L 29/0696 (2013.01);
Abstract

Various embodiments may provide an integrated circuit layout cell. The integrated circuit layout cell may include a doped region of a first conductivity type, a doped region of a second conductivity type opposite of the first conductivity type, and a further doped region of the first conductivity type at least partially within the doped region of the second conductivity type, and continuous with the doped region of the first conductivity type. The integrated circuit cell may include a first transistor having a control terminal, a first controlled terminal, and a second controlled terminal. The first controlled terminal and the second controlled terminal of the first transistor may include terminal regions of the second conductivity type formed within the further doped region of the first conductivity type. The integrated circuit cell may also include a second transistor.


Find Patent Forward Citations

Chong, Kwen. (2023). Integrated circuit layout cell, integrated circuit layout arrangement, and methods of forming the same (U.S. Patent No. 11695011). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11695011

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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