The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2023

Filed:

Mar. 01, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Michihito Kono, Yokkaichi Mie, JP;

Takashi Izumida, Kanagawa, JP;

Tadayoshi Uechi, Kanagawa, JP;

Takeshi Shimane, Chiba, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/40 (2023.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/08 (2013.01); H01L 25/18 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H01L 2224/08145 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A semiconductor memory device, includes: a first region including a memory cell array; and a second region including a peripheral circuit. The second region includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes: a semiconductor region between the first and second surfaces; an n-type semiconductor region provided on the first surface and higher in donor concentration than the semiconductor region; a damaged region provided on the second surface; and a p-type semiconductor region provided between the damaged region and the n-type semiconductor region, closer to the second surface than the n-type semiconductor region in a direction from the first surface toward the second surfaces of the semiconductor substrate, and higher in acceptor concentration than the semiconductor region.


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