The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2023

Filed:

Mar. 19, 2021
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Douglas Michael Reber, Austin, TX (US);

Rishi Bhooshan, Greater Noida, IN;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/58 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/78 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/11462 (2013.01); H01L 2224/11614 (2013.01); H01L 2224/13147 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/14253 (2013.01); H01L 2924/3025 (2013.01); H01L 2924/3512 (2013.01);
Abstract

Wafer processing techniques, or methods for forming semiconductor rides, are disclosed for fabricating plated pillar dies having die-level electromagnetic interference (EMI) shield layers. In embodiments, the method includes depositing a metallic seed layer over a semiconductor wafer and contacting die pads thereon. An electroplating process is then performed to compile plated pillars on the metallic seed layer and across the semiconductor wafer. Following electroplating, selected regions of the metallic seed layer are removed to produce electrical isolation gaps around a first pillar type, while leaving intact portions of the metallic seed layer to yield a wafer-level EMI shield layer. The semiconductor wafer is separated into singulated plated pillar dies, each including a die-level EMI shield layer and plated pillars of the first pillar type electrically isolated from the EMI shield layer.


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