The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2023

Filed:

Sep. 08, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Yuzuru Shibazaki, Fujisawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/32 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01);
Abstract

ABSTRACT A semiconductor memory device provides a first memory cell array including a plurality of first memory blocks, a second memory cell array comprising a plurality of second memory blocks, and a voltage supply line electrically connected to the plurality of first memory blocks and the plurality of second memory blocks. Moreover, this semiconductor memory device is configured to execute a write operation. At a first timing of this write operation, the voltage supply line is not electrically continuous with the first and second memory blocks. Moreover, a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first and second memory blocks is larger than a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first memory block.


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