The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2023

Filed:

Nov. 24, 2021
Applicant:

University-industry Cooperation Group of Kyung Hee University, Yongin-si, KR;

Inventors:

Seung Woo Lee, Seoul, KR;

Jae Hee Jo, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G09G 3/20 (2006.01); H03K 17/687 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/20 (2013.01); G11C 19/28 (2013.01); H03K 17/6871 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2340/0435 (2013.01);
Abstract

A scan driver circuit for an active matrix array includes a plurality of stages and a plurality of decoders that are sequentially driven at different driving timings in a same stage based on a combination of the plural decoder signals or that are driven at the same timing in different stages where a last decoder of the plural decoders sequentially outputs a scan line signal according to a driving state of the plural decoders in each of plural stages, each of the plural decoders includes an input part, an output part and a reset part, and the input part includes a first decoding transistor, a fourth decoding transistor connected to a clock signal and second, third, fifth and sixth decoding transistors connected in series to each of the first decoding transistor and the fourth decoding transistor and connected to the plural decoder signals.


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