The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2023

Filed:

Jun. 23, 2021
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Himanshu Mangal, Agra, IN;

Pankaj Mudgil, Ohtak, IN;

Siddhartha Jain, Noida, IN;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/394 (2020.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/392 (2020.01);
Abstract

An integrated circuit (IC) layout includes various memory blocks arranged in rows and columns, and a memory controller arranged in parallel to one of the rows and the columns. The IC layout further includes metal routes that are created over the memory blocks for coupling the memory and the memory controller and facilitating signal routing therebetween. Each memory block is coupled with the memory controller by way of one or more metal routes. When the memory controller is arranged in parallel to the rows, the one or more metal routes are created over memory blocks that are included in a column, whereas when the memory controller is arranged in parallel to the columns, the one or more metal routes are created over memory blocks that are included in a row.


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