The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2023

Filed:

Jun. 13, 2022
Applicant:

The Regents of the University of California, Oakland, CA (US);

Inventors:

Tae Joon Seok, Berkeley, CA (US);

Ming Chiang A Wu, Moraga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/35 (2006.01); G02B 6/12 (2006.01); G02B 6/293 (2006.01);
U.S. Cl.
CPC ...
G02B 6/3546 (2013.01); G02B 6/3508 (2013.01); G02B 6/12007 (2013.01); G02B 6/29344 (2013.01); G02B 2006/12145 (2013.01);
Abstract

A large-scale single-photonics-based optical switching system that occupies an area larger than the maximum area of a standard step-and-repeat lithography reticle is disclosed. The system includes a plurality of identical switch blocks, each of is formed in a different reticle field that no larger than the maximum reticle size. Bus waveguides of laterally adjacent switch blocks are stitched together at lateral interfaces that include a second arrangement of waveguide ports that is common to all lateral interfaces. Bus waveguides of vertically adjacent switch blocks are stitched together at vertical interfaces that include a first arrangement of waveguide ports that is common to all vertical interfaces. In some embodiments, the lateral and vertical interfaces include waveguide ports having waveguide coupling regions that are configured to mitigate optical loss due to stitching error.


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