The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

Jun. 19, 2020
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventor:

Chun-Sheng Chen, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01G 4/30 (2006.01); H01L 49/02 (2006.01); G06F 30/10 (2020.01);
U.S. Cl.
CPC ...
H01L 28/82 (2013.01); G06F 30/10 (2020.01); H01G 4/306 (2013.01);
Abstract

A multilayer capacitive element and a design method of the same are provided. The capacitive element includes a substrate having a groove, a first aspect ratio modulation structure, and a plurality of conductive layers and a plurality of dielectric layers. The first aspect ratio modulation structure is located in the groove to define the groove as a first region and a first modulation region, wherein an aspect ratio of the first modulation region is different from that of the first region. The plurality of conductive layers and the plurality of dielectric layers are alternately stacked in the groove.


Find Patent Forward Citations

Chen, Chun-Sheng. (2023). Multilayer capacitive element having aspect ratio modulation structure and design method of the same (U.S. Patent No. 11688761). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11688761

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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