The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

Aug. 23, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Jeffrey West, Dallas, TX (US);

Mrinal Das, Allen, TX (US);

Byron Williams, Plano, TX (US);

Thomas Bonifield, Dallas, TX (US);

Maxim Franke, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/52 (2006.01); H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 49/02 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 28/60 (2013.01); H01L 23/3107 (2013.01); H01L 23/4952 (2013.01); H01L 23/49513 (2013.01); H01L 23/49575 (2013.01); H01L 23/5223 (2013.01); H01L 23/5286 (2013.01); H01L 24/05 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05025 (2013.01); H01L 2924/1426 (2013.01);
Abstract

An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.


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