The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

Mar. 02, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Yasunori Iwashita, Yokkaichi Mie, JP;

Shinya Arai, Yokkaichi Mie, JP;

Keisuke Nakatsuka, Kobe Hyogo, JP;

Takahiro Tomimatsu, Nagoya Aichi, JP;

Ryo Tanaka, Yokkaichi Mie, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 24/06 (2013.01); H01L 24/20 (2013.01); H01L 24/82 (2013.01); H01L 2224/06151 (2013.01); H01L 2224/221 (2013.01); H01L 2224/224 (2013.01); H01L 2224/8234 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1438 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes a first chip, and a second chip bonded to the first chip. The first chip includes: a substrate; a transistor provided on the substrate; a plurality of first wirings provided above the transistor; and a plurality of first pads provided above the first wirings. The second chip includes: a plurality of second pads coupled to the plurality of first pads, respectively; a plurality of second wirings provided above the second pads; and a memory cell array provided above the second wirings. The first wiring, the first pad, the second pad, and the second wiring are coupled to one another in series to form a first pattern.


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