The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

May. 31, 2019
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Zhiwei Liang, Beijing, CN;

Wenqian Luo, Beijing, CN;

Yingwei Liu, Beijing, CN;

Ke Wang, Beijing, CN;

Qi Yao, Beijing, CN;

Huijuan Wang, Beijing, CN;

Haixu Li, Beijing, CN;

Zhanfeng Cao, Beijing, CN;

Guangcai Yuan, Beijing, CN;

Xue Dong, Beijing, CN;

Guoqiang Wang, Beijing, CN;

Zhijun Lv, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2023.01); H01L 27/12 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/167 (2013.01); H01L 24/13 (2013.01); H01L 27/124 (2013.01); H01L 2224/13016 (2013.01); H01L 2224/1319 (2013.01); H01L 2224/13083 (2013.01); H01L 2224/13124 (2013.01); H01L 2224/13147 (2013.01);
Abstract

Provided is a display backplate including an array substrate and a plurality of pairs of connection structures on the array substrate, wherein the array substrate includes a plurality of thin-film transistors and a common electrode signal line, wherein at least one of the plurality of thin-film transistors is connected to one of a pair of connection structures and the common electrode signal line is connected to the other of the pair of connection structures; and an area of a first section of the connection structure is negatively correlated with a distance between the first section and a surface of the array substrate, and the first section is parallel to the surface of the array substrate.


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