The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

Jan. 21, 2022
Applicant:

Futurewei Technologies, Inc., Plano, TX (US);

Inventors:

Shiqun Gu, San Diego, CA (US);

Jinghua Zhu, Dongguan, CN;

Hongying Zhang, Shanghai, CN;

Jun Xia, Shenzhen, CN;

Wangsheng Xie, Shenzhen, CN;

Shuangfu Wang, Shanghai, CN;

Hong Liu, Shanghai, CN;

Liming Zhao, Shanghai, CN;

Hongquan Sun, Beijing, CN;

Assignee:

Futurewei Technologies, Inc., Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 23/29 (2006.01); H01L 21/48 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01); H01L 21/683 (2006.01); H01L 25/065 (2023.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/06 (2013.01); H01L 21/486 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/293 (2013.01); H01L 24/03 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 24/81 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 2221/68304 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/81005 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01);
Abstract

An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided to improve integrated circuit power delivery. The integrated circuit package includes a first die having a plurality of pads formed in the first die and exposed on a top surface of the first die, at least one post on the first die, and a substrate including one or more redistribution layers. Each post in the at least one post spans at least two pads on the first die utilized for power distribution, and the first die is connected to the substrate via the at least one post.


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