The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

Nov. 05, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jim Shih-Chun Liang, Poughkeepsie, NY (US);

Baozhen Li, South Burlington, VT (US);

Chih-Chao Yang, Glenmont, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 49/02 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 21/76895 (2013.01); H01L 23/5222 (2013.01); H01L 28/56 (2013.01); H01L 28/90 (2013.01); H01L 23/5226 (2013.01);
Abstract

An integrated circuit structure is provided. The integrated circuit structure includes a back end of line (BEOL) wiring layer including metal lines and a first area between the metal lines. The integrated circuit structure also includes a metal-insulator-metal (MIM) capacitor formed in the first area. The MIM capacitor includes a first electrode, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, a second dielectric layer formed on the second electrode, a third electrode formed on the second dielectric layer, a third dielectric layer formed on the third electrode, a fourth electrode formed on the third dielectric layer, a first metal interconnect electrically connecting the first electrode and the third electrode, and a second metal interconnect electrically connecting the second electrode to the fourth electrode.


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