The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2023
Filed:
Mar. 07, 2022
Integrated Silicon Solution, (Cayman) Inc., Grand Cayman, KY;
Amitay Levi, Cupertino, CA (US);
Dafna Beery, Palo Alto, CA (US);
Andrew J. Walker, Mountain View, CA (US);
Integrated Silicon Solution, (Cayman) Inc., Grand Cayman, KY;
Abstract
A method for manufacturing an inverter circuit includes providing a semiconductor substrate and forming at least one dielectric trench isolation structure in the semiconductor substrate to divide the semiconductor substrate into first and second regions. A P+ doped portion and an N+ doped portion is formed in each of the first and second regions. Gate structure layers are then deposited over the semiconductor substrate. A first opening is formed in the gate structure layers over the P+ doped portion of a first region and a second opening is formed in the gate structure layers over the N+ doped portion of a second region. A gate dielectric layer is then formed on an inner side of the first and second openings. The surface of the semiconductor substrate in the first and second openings is etched. A semiconductor material is formed in the first and second openings by selective epitaxial growth.