The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

Jun. 24, 2020
Applicant:

Idex Biometrics Asa, Oslo, NO;

Inventor:

Matthew Henry, Elkridge, MD (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1045 (2016.01); G06F 9/30 (2018.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 12/0884 (2016.01); G06F 12/109 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1063 (2013.01); G06F 9/30043 (2013.01); G06F 12/0207 (2013.01); G06F 12/0653 (2013.01); G06F 12/0884 (2013.01); G06F 12/109 (2013.01);
Abstract

A cache includes a p-by-q array of memory units; a row addressing unit; and a column addressing unit. Each memory unit has an m-by-n array of memory cells. The column addressing unit has, for each memory unit, m n-to-one multiplexers, one associated with each of the m rows of the memory unit, wherein each n-to-one multiplexer has an input coupled to each of the n memory cells associated with the row associated with that multiplexer. The row addressing unit has, for each memory unit, n m-to-one multiplexers, one associated with each of the n columns of the memory unit, wherein each m-to-one multiplexer has an input coupled to each of the m memory cells associated with the column associated with that multiplexer. The row addressing unit and column addressing unit support reading and/or writing of the array of memory units, e.g. using virtual or physical addresses.


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