The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

May. 09, 2022
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Giby Samson, San Diego, CA (US);

Harshat Pant, San Diego, CA (US);

Keyurkumar Karsanbhai Kansagra, Bangalore, IN;

Mohammed Yousuff Shariff, Hyderabad, IN;

Vinayak Nana Mehetre, Bangalore, IN;

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/56 (2006.01); G06F 1/26 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
G05F 1/56 (2013.01); G06F 1/263 (2013.01); H03K 17/687 (2013.01);
Abstract

A system on chip (SOC) includes a power distribution network (PDN) that has two different types of power multiplexers. The first power multiplexer type includes a lower resistance switching logic, and the second type includes a higher resistance switching logic as well as digital logic to provide an enable signal to the first type of power multiplexer. A given first-type power multiplexer may have multiple power multiplexers of the second type in a loop, the loop including communication paths for the enable signal and feeding the enable signal back to an enable input of the first-type power multiplexer.


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