The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

Sep. 16, 2021
Applicant:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Frédéric Boeuf, Le Versoud, FR;

Cyrille Barrera, Grenoble, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/225 (2006.01); G02F 1/025 (2006.01); G02F 1/035 (2006.01);
U.S. Cl.
CPC ...
G02F 1/2257 (2013.01); G02F 1/025 (2013.01); G02F 1/035 (2013.01); G02F 2202/103 (2013.01);
Abstract

A capacitive electro-optical modulator includes a silicon layer having a cavity having sidewalls and a floor. A germanium or silicon-germanium strip overlies the silicon layer within the cavity. A silicon strip overlies the germanium or silicon-germanium strip within the cavity. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator fills the cavity laterally adjacent the germanium or silicon-germanium strip and the silicon strip and extending between the sidewalls of the cavity. An upper insulating layer overlies the silicon strip and the insulator. A layer of III-V material overlies the upper insulating layer. The layer of III-V material formed as a third strip is arranged facing the silicon strip and separated therefrom by a portion of the upper insulating layer.


Find Patent Forward Citations

Loading…