The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Jun. 07, 2021
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Seung Chan Lee, Hwaseong-si, KR;

Beom Soo Park, Seongnam-si, KR;

Wang Jo Lee, Suwon-si, KR;

Jae Bum Cho, Seoul, KR;

Jae Ik Lim, Hwaseong-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 27/1251 (2013.01); H01L 27/1255 (2013.01); H01L 29/7869 (2013.01); H01L 29/78675 (2013.01);
Abstract

A display device includes: a substrate; a polycrystalline semiconductor layer which includes a first electrode, a channel, and a second electrode of a driving transistor disposed on the substrate; a first gate insulating layer disposed on the polycrystalline semiconductor layer; a gate electrode of the driving transistor which is disposed on the first gate insulating layer and overlaps the channel; a lower first scan line disposed on the first gate insulating layer; a second gate insulating layer disposed on the gate electrode and on the lower first scan line; a first lower boost electrode disposed on the second gate insulating layer; a first interlayer-insulating layer disposed on the first lower boost electrode; an oxide semiconductor layer disposed on the first interlayer-insulating layer and including a first upper boost electrode overlapping the first lower boost electrode; and a first connection electrode connecting the gate electrode and the first upper boost electrode.


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