The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Feb. 25, 2021
Applicant:

Seiko Epson Corporation, Tokyo, JP;

Inventors:

Yukio Okamura, Nagano, JP;

Toru Matsuyama, Nagano, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/18 (2006.01); H01L 23/498 (2006.01); G01R 31/3185 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H05K 1/029 (2013.01); G01R 31/318538 (2013.01); G01R 31/318572 (2013.01); G01R 31/318597 (2013.01); H01L 23/49816 (2013.01); H05K 1/0268 (2013.01); H05K 1/0287 (2013.01); H05K 1/111 (2013.01); H05K 1/181 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10212 (2013.01);
Abstract

There is provided a semiconductor apparatus including a memory controller; a CPU; a high-speed communication controller; a memory operation terminal group that includes a plurality of memory operation terminals for inputting a first signal propagating between an external memory group and the memory controller; a high-speed communication terminal group that includes a plurality of high-speed communication terminals for inputting a second signal to the high-speed communication controller; an inspection terminal group that includes a plurality of inspection terminals for acquiring information from the CPU and performing debugging; and a terminal mounting surface at which the memory operation terminal group, the high-speed communication terminal group, and the inspection terminal group are provided, in which at the terminal mounting surface, a first inspection terminal among the plurality of inspection terminals is located between the memory operation terminal group and the high-speed communication terminal group.


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