The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Sep. 10, 2021
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Christopher D. Finan, Cupertino, CA (US);

Alexander Ukanwa, Morgan Hill, CA (US);

Charles F. Dominguez, San Carlos, CA (US);

Jean-Didier Allegrucci, Sunnyvale, CA (US);

Jeffrey J. Irwin, Cupertino, CA (US);

Kalpana Bansal, San Jose, CA (US);

Michael Bekerman, Los Gatos, CA (US);

Remi Clavel, Milpitas, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0016 (2013.01); G06F 1/12 (2013.01); H04L 7/0008 (2013.01);
Abstract

A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.


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