The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Aug. 14, 2020
Applicant:

Tmy Technology Inc., Taipei, TW;

Inventors:

Su-Wei Chang, Taipei, TW;

Chueh-Jen Lin, Taipei, TW;

Wen-Tsai Tsai, Taipei, TW;

Tzu-Chieh Hung, Taipei, TW;

Yang Tai, Taipei, TW;

Chien-Tse Fang, Taipei, TW;

Po-Chia Huang, Taipei, TW;

Te-Liang Sun, Taipei, TW;

Ying-Yen Lu, Taipei, TW;

Assignee:

TMY Technology Inc., Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01P 5/02 (2006.01); H01P 3/08 (2006.01); H01Q 13/02 (2006.01); H01Q 19/185 (2006.01); H01Q 21/29 (2006.01); H04B 17/00 (2015.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
H01P 5/028 (2013.01); G01R 31/2822 (2013.01); H01P 3/082 (2013.01); H01P 3/088 (2013.01); H01P 5/02 (2013.01); H01Q 13/02 (2013.01); H01Q 19/185 (2013.01); H01Q 21/293 (2013.01); H04B 17/0085 (2013.01);
Abstract

An antennas-in-package (AiP) verification board is provided, which includes a carrier board configured for disposing an antenna array or an electronic circuit; and a plurality of SMPM connectors. The plurality of SMPM connectors are arranged in an array on the carrier board and electrically connected with the antenna array or the electronic circuit of the carrier board for testing the characteristics of the antenna array on the carrier board or the characteristics of the electronic circuit on the carrier board. The AiP verification board is fixed on a beamforming test platform. In addition to the aforementioned AiP verification board, an AiP verification board including a plurality of adaptor structures and an AiP verification board including a plurality of connectors and a plurality of adaptor structures are also provided.


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