The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Aug. 06, 2021
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Yung-Fung Lin, Taoyuan, TW;

Yu-Chieh Chou, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 29/417 (2006.01); H01L 29/20 (2006.01); H01L 29/778 (2006.01); H01L 21/306 (2006.01); H01L 29/205 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66462 (2013.01); H01L 21/0254 (2013.01); H01L 21/30621 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/4175 (2013.01); H01L 29/7787 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01);
Abstract

A method of fabricating a semiconductor structure includes forming a GaN-based semiconductor layer on a substrate, forming a silicon-containing insulating layer on the GaN-based semiconductor layer, forming a recess in the silicon-containing insulating layer in a first etching step, wherein the first etching step is performed by using a fluorine-containing etchant and applying a first bias power, and enlarging the recess to extend into the GaN-based semiconductor layer in a second etching step, wherein the second etching step is performed by using the same fluorine-containing etchant as the first etching step and applying a second bias power that is greater than the first bias power. In addition, a method of fabricating a high electron mobility transistor is provided.


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