The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2023
Filed:
May. 26, 2021
Infineon Technologies Dresden Gmbh & Co. KG, Dresden, DE;
Ahmed Mahmoud, Freising, DE;
Franz Hirler, Isen, DE;
Marco Mueller, Pirna, DE;
Rolf Weis, Dresden, DE;
Infineon Technologies Dresden GmbH & Co. KG, Dresden, DE;
Abstract
A semiconductor device includes a layer stack with first semiconductor layers and second semiconductor layers of opposite doping types arranged alternatingly. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers, and has a first end arranged in a first region of the first semiconductor device and extends from the first end into a second region of the first semiconductor device. Second semiconductor regions of the first semiconductor device adjoin at least one of the second semiconductor layers. A third semiconductor region of the first semiconductor device adjoins the first semiconductor layers. The first semiconductor region extends from the first region into the second region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions. An average doping concentration along a shortest path between the first and third semiconductor regions in at least one of the first or second semiconductor layers in the first region differs from an average doping concentration along a shortest path between the first and third semiconductor regions of the same layer in the second region.