The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Jun. 22, 2020
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Michael Niendorf, Verl, DE;

Ludwig Busch, Erwitte, DE;

Oliver Markus Kreiter, Warstein, DE;

Christian Neugirg, Regensburg, DE;

Ivan Nikitin, Regensburg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 23/4952 (2013.01); H01L 23/49503 (2013.01); H01L 23/49562 (2013.01); H01L 23/49568 (2013.01); H01L 24/48 (2013.01); H01L 2224/48137 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/13055 (2013.01);
Abstract

A power semiconductor module includes a leadframe having a first die pad, a second die pad separated from the first die pad, a first power lead formed as an extension of the first die pad, a second power lead separated from the first and second die pads, and a first connection region formed as an extension of the second power lead alongside the second die pad. A first plurality of power semiconductor dies is attached to the first die pad and electrically coupled in parallel. A second plurality of power semiconductor dies is attached to the second die pad and electrically coupled in parallel. A first electrical connection extends between the first plurality of power semiconductor dies and the second die pad in a first direction. A second electrical connection extends between the second plurality of power semiconductor dies and the first connection region in the first direction.


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