The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Oct. 21, 2020
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Venkata Sharat Chandra Parimi, Sunnyvale, CA (US);

Satish Radhakrishnan, San Jose, CA (US);

Diwakar Kedlaya, San Jose, CA (US);

Fang Ruan, Milpitas, CA (US);

Amit Bansal, Milpitas, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01J 37/32 (2006.01); B08B 7/00 (2006.01);
U.S. Cl.
CPC ...
H01J 37/32862 (2013.01); B08B 7/0035 (2013.01); H01J 37/32715 (2013.01);
Abstract

Semiconductor processing systems according to embodiments of the present technology may include a chamber body having sidewalls and a base. The chamber body may define an internal volume. The systems may include a substrate support assembly having a shaft and a platen coupled with the shaft along a first surface of the platen. The semiconductor processing systems may include a cover plate positioned on the platen of the substrate support assembly along a second surface of the platen opposite the first surface. The cover plate may include a flange extending about an exterior region of the cover plate. The flange may be in direct contact with the platen. The cover plate may include an upper wall vertically offset from the flange. An interior volume may be defined between the upper wall and the platen of the substrate support assembly.


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