The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Jul. 14, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyeok Jun Choi, Suwon-si, KR;

Young Chul Cho, Seongnam-si, KR;

Seung Jin Park, Hwaseong-si, KR;

Jae Woo Park, Yongin-si, KR;

Young Don Choi, Seoul, KR;

Jung Hwan Choi, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); H03L 7/081 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/1057 (2013.01); G11C 7/1084 (2013.01); H03L 7/0814 (2013.01);
Abstract

A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.


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