The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2023
Filed:
Jan. 12, 2021
Sub-fpga level compilation platform with adjustable dynamic region for emulation/prototyping designs
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Xiaojian Yang, Santa Clara, CA (US);
Frederic Revenu, San Carlos, CA (US);
Dinesh D. Gaitonde, Fremont, CA (US);
Amit Gupta, Los Altos, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/343 (2020.01); G06F 30/347 (2020.01);
U.S. Cl.
CPC ...
G06F 30/343 (2020.01); G06F 30/347 (2020.01);
Abstract
A method of FPGA compilation for an emulation system includes receiving a netlist for an FPGA, partitioning the netlist into a set of sub-FPGA netlists, and mapping each of the sub-FPGA netlists in the set to a corresponding dynamic sub-FPGA region of the FPGA. The method further includes implementing the sub-FPGA netlists of the set in parallel to obtain a corresponding set of sub-FPGA bitstreams.