The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Mar. 29, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Riyas Noorudeen Remla, Singapore, SG;

Chee Chong Chan, Singapore, SG;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/333 (2020.01); G06F 30/31 (2020.01); G06F 119/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/333 (2020.01); G06F 30/31 (2020.01); G06F 2119/02 (2020.01);
Abstract

A semiconductor device comprises a design under test (DUT), a testing interface, pattern generation circuitry, and pattern checker circuitry. The pattern generation circuitry is connected to the DUT and the testing interface. The pattern generation circuitry is configured to generate a test data sequence and control data based on configuration data received from the testing interface, and communicate the test data sequence and the control data to the DUT. The pattern checker circuitry is connected to the DUT and the testing interface. The pattern checker circuitry is configured to generate a comparison test sequence based on the configuration data received from the testing interface, receive resultant test data sequence and output control data from the DUT, and generate a first error signal based on a comparison of the resultant test data sequence and the comparison test sequence and a comparison of the output control data and the configuration data.


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